The present invention relates generally to method and apparatus for sensing data in a memory device such as flash memory integrated circuit. More particularly, the present invention relates to a two-stage pipelined sensing technique for a page mode flash memory.
Memory integrated circuits provide storage and retrieval of data. There are several types of memory, including, generally, volatile and nonvolatile memory. Nonvolatile memory includes EPROM, EEPROM and flash memory technology. In general, an address is provided to the memory while data is read or stored at the location in the memory defined by the address. General design goals for all memory devices include large storage size, short access times for reading and writing of data, and minimized power dissipation.
One design technique to reduce read access time is page mode operation. In page mode, an entire page of data is simultaneously sensed internally to the memory. The address to the chip may then be changed to read individual words on the address page. In one example, four 16-bit words form a page. Sixty four bits are sensed and then read one word or sixteen bits at a time from the memory. Sensing such a large number of bits simultaneously can cause operational problems within the memory. The current drain due to the read current in the example mentioned is approximately 80 .mu.A per bit. For sensing 64 bits, the total read current is 5.12 mA. This read current is a substantial component of the power dissipation for the entire chip. Switching this current can introduce transient voltages on the power and ground nodes of the chip. These transient voltages can introduce delay in the circuit performance and corrupted data. Accordingly, there is a need for an improved method and apparatus for sensing data in a page mode memory device.